The present invention is generally directed to a system and method for built-in self test (BIST) of a fabricated Integrated Circuit (IC) device to ensure proper operation thereof. With steadily increasing IC complexity, fabrication quantities, and IC reliance, there is an ever increasing need to verify proper operation of ICs without overly burdensome time and equipment requirements. Moreover, these verification measures should tolerate some uncertainties in the IC and yet still provide assurance of proper operation. Further still, verification measures should be resilient to changing operational parameters encountered after fabrication. Previous attempts in the art have not provided suitable measures.
Attempts have been made in the art within the fabrication and packaging facilities themselves to physically connect external automated testing equipment (ATEs) to input and output ports of ICs to stream known inputs and measure the outputs of the ICs. However, such an approach requires complicated physical mating or probing by testing equipment in clean room environments to each port of an IC and fails to suitably address on-going IC validation after deployment in the field with changing operational circumstances such as clock speed. For example, an IC used as a brake controller in an automobile cannot be continuously validated once the external testing apparatus has been disconnected and the IC has left the clean-room. However, validation of proper operation continuously, especially after the IC has left fabrication and is employed in the field is necessary, especially in light of changing operational conditions.
There is therefore a need for a system and method by which X-values (which may be unknown, indeterminate, out of bound, or other unexpected values—as opposed to standard expected values such as “0” and “1”) may be selectively bit-wise masked without an undue loss of substantive operational diagnostic data and without undue added chip resources. There is therefore a need for a system and method by which bit-wise selective mask patterns may be generated and maintained on the IC and applied to the scan results of plural scan iterations to effectively prevent X-values from propagating into a functional fingerprint of the IC. There is therefore a need for a system and method of self test that is resilient and extensible across changing operational parameters encountered after fabrication of the IC.